A continuing trend in the semiconductor field is the increase in the density of storage bits per chip in semiconductor memory devices. This trend has continued for high density, medium performance, memories such as dynamic random access memories (dRAMs). In the past decade, each new generation of dRAM has provided an increase in storage capacity of a factor of four over the prior generation, with the newest generation of chips containing 4 Mbits each. The rapid increase of the density of such memories has created increased pressure to increase memory bandwidth, i.e., the speed at which the user can access the bits in the memory. Without improvement of memory bandwidth along with the increase in the density of the memory, the additional bits provided by a new memory generation have decreasing utility to the user.
This bandwidth pressure has also led to increased emphasis on increasing the density and also the performance of static random access memories (sRAMs) which can be used not only for main memory in a system, but also as large high speed caches in a memory system. With the advent of high performance CMOS and BiCMOS process technologies, high density sRAMs with access times less than 10 nsec have been fabricated, as described in Tran et al., "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size," 1989 IEEE ISSCC Digest of Technical Papers (IEEE, 1989), pp. 36-37. sRAM devices such as these can be used not only for main memory in a system, but also as large high speed caches in a memory system.
As is well known, a cache memory is a common technique used in data processing systems for improvement of system memory performance. A cache memory is a relatively small and high-speed memory which stores data from a number of main memory locations surrounding a memory location which has been addressed. The theory of cache operation is that the system central processing unit (CPU) will frequently address a memory location which is adjacent, or near (in terms of address value), a memory location that it has recently addressed. Each group of data stored in the cache is associated with a "tag", or a portion of the memory address which is common to the data stored in the cache, and a comparator compares a portion of the memory address presented by the CPU with the tag or tags associated with the data stored in the cache. If the desired memory address matches a tag value (i.e., a cache "hit" occurs), the cache can be accessed to more quickly provide the desired data than if the main memory were addressed, thereby improving the effective memory bandwidth of the system.
In the event that the appropriate portion of the desired memory address does not match the tags associated with the data stored in the cache (i.e., a cache "miss" occurs), the main memory must be accessed, resulting in a delay relative to a cache access. Generally a portion of the cache is then refilled with data from main memory in the locations proximate to the newly addressed main memory location. The additional time required to access main memory instead of the cache, plus the additional time required to fill the cache with the new data from the proximate addresses to the new memory address (if done for each miss), is commonly referred to as the "miss penalty". It should be noted that the time required to refill the cache, as well as the initial access to main memory for the desired memory address, depends upon the main memory cycle time, and is directly proportional to the number of bits in the cache (or portion of the cache associated with a given tag, such portion commonly referred to as a "line" of the cache). As a result, if the miss penalty becomes large, the effective memory bandwidth of the system will decrease, even with relatively low miss rates. In improving the system performance by improving the cache bandwidth, it is therefore important not only to reduce the rate of cache misses, but also to reduce the miss penalty associated with each cache miss.
It is desired, for purposes of reducing system cost, as well as system complexity, to incorporate cache accesability within the main memory device itself in order to reduce the miss penalty. It has been proposed that dRAMs having the static column decode feature be used in a cache organization. See J. Goodman and M-C Chiang, "The use of Static Column RAM as a Memory Hierarchy," The 11th Annual Symposium on Computer Architecture (IEEE Computer Society Press, 1984), pp. 167-74. However, a cache miss in such a memory will require that the dRAM operation of precharging the dynamic row decoding and sense circuitry, followed by presentation of a row address together with a row address strobe be performed prior to the access of a bit associated with the new row address. It should be noted that dRAMs such as this have multiplexed address pins, so that the presentation of the column address must wait until after the presentation of the row address. Accordingly, the time penalty for such an operation in the event of a cache miss reduces the benefits of using such a memory in a "cache" mode.
Due to the non-multiplexed and static (i.e., non-clocked) operation of conventional sRAMs, the disadvantages of using static column decode dRAMs as an integrated memory with on-chip cache can be somewhat reduced. This is especially the case for some conventional sRAM devices which utilize address transition detectors for detecting a change in the address presented thereto, so that decoding of the address need only occur when a new address is received. In addition, for those static memories which utilize some dynamic features, such as bit line precharge and dynamic address decoding, these dynamic operations will be initiated by the address transition detection circuitry so that they are done only in the event of a memory address transition.
In conventional memories which utilize address transition detection, however, a change of address will cause the memory to precharge and to decode the address even for those cycles for which the row address does not change. For the example of a 64kbit sRAM having 256 rows and 256 columns, where a single column is associated with a single sense amplifier, a large number of bits (e.g., 256 bits in a 64 kbit memory) are potentially accessible from a single row. However, if address transition detection is performed on the entire address, as is conventionally done, a full memory cycle will be performed in such conventional memories even when the desired data is already present in the sense amplifiers, and when precharge and row address decoding is unnecessary.
The performance of a full memory cycle will dissipate more power than will a cycle consisting of column decode and output of the state of the selected sense amplifier, since the full memory cycle includes additional operations such as precharge, energizing of the selected row, and sensing. Accordingly, if a full memory cycle is not performed in those instances when only an access of previously sensed data from a previously selected row is desired, the power dissipation of the memory, measured over normal system operation, can be reduced.
It is therefore an object of this invention to provide a memory which allows for faster bit access from a previously sensed row, without requiring a new row to be selected and sensed.
It is a further object of this invention to provide such a memory using address transition detection on only a portion of the memory address for initiating a precharge portion of the cycle, so that a faster access mode is available for the data bits accessible by transitions of the remainder of the memory address.
It is a further object of this invention to provide such a memory wherein the address transition detection can be disabled, ensuring that the memory remains in the fast access, or cache, mode.
It is a further object of the invention to provide such a memory which is organized into blocks, each having cache operation therefrom, to improve the cache hit performance of the memory.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the instant specification together with the drawings.